1. Field of the Invention
This invention relates generally to an encoder circuit, and in particular to an encoder circuit for encoding a plurality of parallel input signals into encoded data in a predetermined form to be fed out on a plurality of output lines, by ascertaining the critical level at which the input signals change from a high level to a low level and vice versa.
2. Description of the Background Art
In order to have a background understanding of the invention, reference is made to FIG. 3 which illustrates the configuration of a typical prior-art encoder circuit. The illustrated circuit functions to find out the critical level at which input signals D.sub.1 -D.sub.2 change from a high or "H" level to a low or "L" level, and convert them into binary-coded output signals, which are fed out on output lines L1-L3. The input signals D.sub.1 -D.sub.7 are of such nature that, if some input signals Di (where i=1-7) are at the "H" level, other signals Dj (where i&gt;j) are all at the "H" level, and that if input signals Di are at "L" level, then other input signals Dk (where i&lt;k) are all at the "L" level. It is noted that these relations are valid when the high and low level conditions are reversed with each other. The encoder circuit of FIG. 3 performs the desired encoding function by finding the critical level at which the input signals turn from the "H" level to the low level or vice versa. Among the circuit devices which generates signals of the nature similar to the input signals D.sub.1 -D.sub.7 is a comparator assembly in the flash A/D converter.
As shown in FIG. 3, if the source potential at one input of the NAND gate A.sub.7 is set as an inverted input signal D.sub.8, and the source potential at the other input of the NAND gate A.sub.0 is set as an input signal D.sub.0, an input signal D.sub.i and an inverted input signal D.sub.i+1 are supplied to NAND gates A.sub.i (where i=0-7) among the NAND gates A.sub.0 -A.sub.7. In other words, each of the NAND gates A.sub.0 -A.sub.7 is supplied with a non-inverted input signal in the series of input signals D.sub.0 -D.sub.8 and an inverted signal of an input signal succeeding to the non-inverted input signal.
The output signals of the NAND gate A.sub.i (where i=0-7) is supplied out in conformity with 3-bit binary data as follows.
(1) When an "1" level output is to be supplied on each output line L.sub.j (j=1-3), the output of the NAND gate A.sub.i is fed out to the gate of a p-channel MOS transistor whose source is connected to the source potential and whose drain is coupled to the output line Lj.
(2) when an "0" level output is to be supplied on each output line L.sub.j, the output of the NAND gate A.sub.i is fed out via an inverter I.sub.i to the gate of an n-channel MOS transistor whose source is coupled to ground potential and whose drain is connected to the output line L.sub.j.
In this manner, for example, when only the output of the NAND gate A.sub.4 is at "L" level, the "100" signal is supplied out on the output lines L3, L2 and L1. Thus, the output from the NAND gate A.sub.4 is applied to the gate of a p-channel MOS transistor whose source is coupled to the supply voltage and whose drain is connected to the output line L3. The output from the NAND gate A.sub.4 is also applied via the inverter I.sub.4 to the gate of an n-channel MOS transistor whose source is coupled to ground potential and whose drain is linked to the output line L2 (or L1).
With this arrangement, regarding the outputs from the NAND gates A.sub.0 -A.sub.7 as intermediate signals, the relations among the input signals, intermediates signals and output signals are expressed as in the Table 1.
TABLE 1 __________________________________________________________________________ Input Intermediate Signal Output (D.sub.0) D.sub.1 D.sub.2 D.sub.3 D.sub.4 D.sub.5 D.sub.6 D.sub.7 (D.sub.8) A.sub.0 A.sub.1 A.sub.2 A.sub.3 A.sub.4 A.sub.5 A.sub.6 A.sub.7 B.sub.3 B.sub.2 B.sub.1 __________________________________________________________________________ 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 1 1 1 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 1 1 0 1 1 1 1 0 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 1 1 1 1 0 0 1 1 1 1 1 1 0 0 0 1 1 1 1 1 0 1 1 1 0 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 __________________________________________________________________________
For example, if the input signals D.sub.0 -D.sub.8 are coded [111110000], then, as represented in the Table 1, only the output of the NAND gate A.sub.4 takes on the "L" level (or "0"), and the outputs from the remaining NAND gates A.sub.0 -A.sub.3 and A.sub.5 -A.sub.7 all assume the "H" level (or "1").
Consequently, the p-channel MOS transistor which is supplied with the output from the NAND gates A.sub.4 at its gate as well as the n-channel MOS transistor which is supplied with the output of the same NAND gate A.sub.4 at its gate through the inverter I.sub.4 is turned on, rendering the output line L3 at the "H" level and the output lines L2 and L1 at the "L" level. Under the conditions, the binary data coded "100" are obtained on the output lines L3-L1 as shown in the Table 1.
For purpose of simplicity and clarity, a 7-segmented (3-bit) encode circuit is illustrated in FIG. 3. However, the actual design of the circuit involves a higher degree or level of segmentation.
With the conventional arrangement of the encoded circuit, it is necessary to provide N+1 NAND gates and inverters for N pairs of input signals (in the form of inverted and non-inverted signals). In short, additional NAND gates and inverters are required for the proper encoding function, which results in larger power consumption. Also, the NAND gates and inverters incorporated in the encoder circuit tend to delay the signal transfer, retarding the encoding operation of the circuit.